eZ80L92 MCU
Product Specification
47
Table 12. Vectored Interrupt Operation (Continued)
Memory
Mode
ADL MADL
Bit
Bit Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
ADL Mode
1
1
•
•
•
•
•
IEF1 ← 0
IEF2 ← 0
The starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
•
•
•
•
•
The ADL mode bit remains set to 1.
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}.
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
The ending Program Counter is { 00h, PC[15:0] }.
The interrupt service routine must end with RETI.L
Non-maskable Interrupts
An active Low input on the NMI pin generates an interrupt request to the eZ80 CPU. This
non-maskable interrupt is always serviced by the eZ80 CPU, regardless of the state of the
Interrupt Enable flags (IEF1 and IEF2). The non-maskable interrupt is prioritized higher
than all maskable interrupts. The response of the eZ80 CPU to a non-maskable interrupt is
described in detail in eZ80® CPU User Manual (UM0077).
PS013015-0316
Interrupt Controller
ZILOG [ ZILOG, INC. ]
