eZ80L92 MCU
Product Specification
48
Chip Selects and Wait States
The ZLP12840 MCU generates four Chip Selects for external devices. Each Chip Select is
programmed to access either memory space or I/O space. The Memory Chip Selects can
be individually programmed on a 64 KB boundary. Each I/O Chip Select can choose a
256-byte section of I/O space. In addition, each Chip Select can be programmed for up to
7 wait states.
Memory and I/O Chip Selects
Each of the Chip Selects is enabled for either the memory address space or the I/O address
space, but not both. To select the memory address space for a particular Chip Select,
CSx_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
Chip Select, CSx_IO must be set to 1. After RESET, the default is for all Chip Selects to
be configured for the memory address space. For either the memory address space or the
I/O address space, the individual Chip Selects must be enabled by setting CSx_EN
(CSx_CTL[3]) to 1.
Memory Chip Select Operation
Operation of each Memory Chip Selects is controlled by three control registers. To enable
a particular Memory Chip Select, following conditions must be fulfilled:
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The Chip Select is enabled by setting CSx_EN to 1.
The Chip Select is configured for Memory by clearing CSx_IO to 0.
The address is in the associated Chip Select range:
CSx_LBR[7:0]
≤ ADDR[23:16] ≤ CSx_UBR[7:0]
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•
No higher priority (lower number) Chip Select meets the above conditions.
A memory access instruction must be executing.
If all the above conditions are met to generate a Memory Chip Select, then the following
actions occur:
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•
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The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low).
MREQ is asserted (driven Low).
Depending upon the instruction, either RD or WR is asserted (driven Low).
If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular Chip Select is valid for a single 64 KB page.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
