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EZ80L92AZ020SC00TR 参数 Datasheet PDF下载

EZ80L92AZ020SC00TR图片预览
型号: EZ80L92AZ020SC00TR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT ROMLESS 100LQFP]
分类和应用:
文件页数/大小: 238 页 / 1067 K
品牌: ZILOG [ ZILOG, INC. ]
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eZ80L92 MCU  
Product Specification  
42  
edge-triggered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the  
edge-detected interrupt. You must set the bit in the Port x Data register to 1 before entering  
either single or dual edge-triggered interrupt mode for that port pin.  
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising  
and a falling edge on the pin cause an interrupt request to be sent to the eZ80 CPU.  
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in  
the Port x Data register determines if a positive or negative edge causes an interrupt  
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt  
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate  
an interrupt request for rising edges.  
GPIO Control Registers  
The 12 GPIO Control Registers operate in groups of four with a set for each Port (Ports B,  
C, and D). Each GPIO port features a Port Data register, Port Data Direction register, Port  
Alternate register 1, and Port Alternate register 2.  
Port x Data Registers  
When the port pins are configured for one of the output modes, the data written to the  
Port x Data Registers (see Table 7) are driven on the corresponding pins. In all modes,  
reading from the Port x Data registers always returns the current sampled value of the  
corresponding pins. When the port pins are configured as edge-triggered interrupt sources,  
writing 1 to the corresponding bit in the Port x Data register clears the interrupt signal that  
is sent to the eZ80 CPU. When the port pins are configured for edge-selectable interrupts  
or level-sensitive interrupts, the value written to the Port x Data register bit selects the  
interrupt edge or interrupt level. See Table 6.  
Table 7. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR =  
00A2h)  
Bit  
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
Reset  
CPU Access  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Note: X = Undefined; R/W = Read/Write.  
PS013015-0316  
General-Purpose Input/Output  
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