eZ80L92 MCU
Product Specification
33
Reset
RESET Operation
The RESET controller within the ZLP12840 MCU provides a consistent system reset
(RESET) function for all type of resets that may affect the system. Following four events
can cause a RESET:
•
•
•
•
External RESET pin assertion.
Watchdog Timer (WDT) time-out when configured to generate a RESET.
Real time clock alarm with eZ80 CPU in low-power SLEEP mode.
Execution of a Debug RESET command.
During RESET, an internal RESET mode timer holds the system in RESET for
257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of all RESET events (RESET pin, WDT,
real time clock, and Debugger)
Note: You must determine if 257 SCLK cycles provides sufficient time for the primary crystal
oscillator to stabilize.
RESET, through the external RESET pin, must always be executed following application
of power (VDD ramp). Without the RESET, following power-up, proper operation of the
ZLP12840 cannot be guaranteed.
PS013015-0316
Reset
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