eZ80L92 MCU
Product Specification
35
The eZ80 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
Non-maskable interrupt (NMI).
Maskable interrupt.
RESET through the external RESET pin driven Low.
Watchdog Timer time-out (if configured to generate either an NMI or RESET upon
time-out).
•
RESET through execution of a Debug RESET command.
To minimize current in HALT mode, the system clock must be disabled for all unused on-
chip peripherals through the Clock Peripheral Power-Down Registers.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See Table 4 and Table 5.
PS013015-0316
Low-Power Modes
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