eZ80L92 MCU
Product Specification
37
Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position
Value Description
7
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
PHI_OFF
6
Reserved.
5
System clock to PRT5 is powered down.
System clock to PRT5 is powered up.
System clock to PRT4 is powered down.
System clock to PRT4 is powered up.
System clock to PRT3 is powered down.
System clock to PRT3 is powered up.
System clock to PRT2 is powered down.
System clock to PRT2 is powered up.
System clock to PRT1 is powered down.
System clock to PRT1 is powered up.
System clock to PRT0 is powered down.
System clock to PRT0 is powered up.
PRT5_OFF
4
PRT4_OFF
3
PRT3_OFF
2
PRT2_OFF
1
PRT1_OFF
0
PRT0_OFF
PS013015-0316
Low-Power Modes
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