eZ80L92 MCU
Product Specification
36
Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1 = 00DBh)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position
Value Description
7
1
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
GPIO_D_OFF
0
1
System clock to GPIO Port D is powered up.
6
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
GPIO_C_OFF
0
1
System clock to GPIO Port C is powered up.
5
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
GPIO_B_OFF
0
System clock to GPIO Port B is powered up.
Reserved.
4
3
1
0
1
0
1
0
1
0
System clock to SPI is powered down.
System clock to SPI is powered up.
SPI_OFF
2
2
System clock to I C is powered down.
2
I2C_OFF
System clock to I C is powered up.
1
System clock to UART1 is powered down.
System clock to UART1 is powered up.
UART1_OFF
0
System clock to UART0 and IrDA endec is powered down.
System clock to UART0 and IrDA endec is powered up.
UART0_OFF
PS013015-0316
Low-Power Modes
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