eZ80L92 MCU
Product Specification
151
2
I C Registers
Addressing
The processor interface provides access to six 8-bit registers: four Read/Write registers,
one Read-Only register and two Write-Only registers, as indicated in Table 80.
Table 80. I2C Register Descriptions
Register
I2C_SAR
I2C_XSAR
I2C_DR
Description
Slave address register
Extended slave address register
Data byte register
I2C_CTL
I2C_SR
Control register
Status register (Read-Only)
Clock Control register (Write-Only)
Software reset register (Write-Only)
I2C_CCR
I2C_SRR
Resetting the I2C Registers
Hardware reset. When the I2C is reset by a hardware reset of the ZLP12840, the
I2C_SAR, I2C_XSAR, I2C_DR and I2C_CTL registers are cleared to 00h; while the
I2C_SR register is set to F8h.
Software Reset. Perform a software reset by writing any value to the I2C Software Reset
Register (I2C_SRR). A software reset sets the I2C back to idle and the STP, STA, and
IFLG bits of the I2C_CTL register to 0.
I2C Slave Address Register
The I2C_SAR register provides the 7-bit address of the I2C when in SLAVE mode and
allows 10-bit addressing in conjunction with the I2C_XSAR register. I2C_SAR[7:1] =
sla[6:0] is the 7-bit address of the I2C when in 7-bit SLAVE mode. When the I2C receives
this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corresponds to
the first bit received from the I2C bus.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 81.
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
