eZ80L92 MCU
Product Specification
149
Table 79. I2C Master Receive Status Codes For Data Bytes
2
2
Code
I C State
Data byte received, Read DATA, clear IFLG,
ACK transmitted clear AAK = 0
MCU Response
Next I C Action
50h
Receive data byte,
transmit NACK
Or read DATA, clear IFLG, Receive data byte,
set AAK = 1
transmit ACK
58h
Data byte received, Read DATA, set STA,
NACK transmitted clear IFLG
Transmit repeated START
Or read DATA, set STP,
clear IFLG
Transmit STOP
Or read DATA, set
STA & STP, clear IFLG
Transmit STOP then
START
38h
Arbitration lost in
NACK bit
Same as master transmit
Same as master transmit
When all bytes are received, a NACK should be sent, then the processor should write a 1
to the STP bit in the I2C_CTL register. The I2C then transmits a STOP condition, clears
the STP bit and returns to the idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I2C enters SLAVE TRANSMIT mode when it receives its own slave address and a
Read bit after a START condition. The I2C then transmits an acknowledge bit (if the AAK
bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register con-
tains the status code A8h.
When I2C contains a 10-bit slave address (signified by F0h–F7h in the I2C_SAR regis-
ter), it transmits an acknowledge after the first address byte is received after a restart. An
interrupt is generated, IFLG is set but the status does not change. No second address byte
is sent by the master. It is up to the slave to remember it had been selected prior to the
restart.
Note:
I2C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code B0h in the I2C_SR register.
The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit
cleared. After the I2C transmits the byte and receives an acknowledge, the IFLG bit is set
and the I2C_SR register contains B8h. When the final byte to be transmitted is loaded into
the I2C_DR register, the AAK bit is cleared when the IFLG is cleared. After the final byte
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
