eZ80L92 MCU
Product Specification
148
Table 78. I2C Master Receive Status Codes (Continued)
2
2
Code
I C State
MCU Response
Next I C Action
48h
Addr + R
For a 7-bit address:
Transmit repeated
START
transmitted, ACK not Set STA, clear IFLG
received
Or set STP, clear IFLG
Transmit STOP
Or set STA & STP,
clear IFLG
Transmit STOP then
START
For a 10-bit address:
Transmit extended
Write extended address byte address byte
to DATA, clear IFLG
38h
68h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Transmit START when
bus is free
Arbitration lost,
SLA+W received,
ACK transmitted
Clear IFLG, clear AAK = 0
Receive data byte,
transmit NACK
Or clear IFLG, set AAK = 1 Receive data byte,
transmit ACK
78h
B0h
Arbitration lost,
General call addr
received, ACK
transmitted
Same as code 68h
Same as code 68h
Arbitration lost,
SLA+R received,
ACK transmitted
Write byte to DATA,
clear IFLG, clear AAK = 0
Transmit last byte,
receive ACK
Or write byte to DATA,
clear IFLG, set AAK = 1
Transmit data byte,
receive ACK
Note: R = Read bit; in essence, the lsb is set to 1.
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
address again, but with the Read bit. The status code then becomes 40h or 48h. It is the
responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is 10h instead of 08h.
After each data byte is received, the IFLG is set and one of the status codes listed in
Table 79 is in the I2C_SR register.
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
