eZ80L92 MCU
Product Specification
147
Table 77. I2C Master Transmit Status Codes For Data Bytes (Continued)
2
2
Code I C State
MCU Response
Next I C Action
30h
Data byte transmitted, Same as code 28h
ACK not received
Same as code 28h
38h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Transmit START when bus
free
When all bytes are transmitted, the processor should write a 1 to the STP bit in the
I2C_CTL register. The I2C then transmits a STOP condition, clears the STP bit and returns
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I2C receives a number of bytes from a slave transmit-
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code 08h is
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in Table 78 is in the
I2C_SR register.
Table 78. I2C Master Receive Status Codes
2
2
Code
I C State
MCU Response
Next I C Action
40h
Addr + R
transmitted, ACK
received
For a 7-bit address,
clear IFLG, AAK = 0
Receive data byte,
transmit NACK
Or clear IFLG, AAK = 1
Receive data byte,
transmit ACK
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
Transmit extended
address byte
Note: R = Read bit; in essence, the lsb is set to 1.
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
