eZ80L92 MCU
Product Specification
155
Bit
Position
Value Description
2
7
IEN
0
1
0
I C interrupt is disabled.
2
I C interrupt is enabled.
2
6
The I C bus (SCL/SDA) is disabled and all inputs are
ignored.
ENAB
2
1
0
The I C bus (SCL/SDA) is enabled.
5
Master mode START condition is sent.
STA
1
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
4
0
STP
1
Master mode stop-transmit STOP condition on the bus.
2
3
0
I C interrupt flag is not set.
IFLG
2
1
I C interrupt flag is set.
2
AAK
0
Not Acknowledge.
Acknowledge.
Reserved.
1
[1:0]
00
I2C Status Register
The I2C_SR register is a Read-Only register that contains a 5-bit status code in the five
most significant bits: the three least significant bits are always 0. The Read-Only I2C_SR
registers share the same I/O addresses as the Write-Only I2C_CCR registers. See Table 85.
Table 85. I2C Status Registers (I2C_SR = 00CCh)
Bit
7
1
6
1
5
1
4
1
3
1
2
0
1
0
0
0
Reset
CPU Access
Note: R = Read only.
R
R
R
R
R
R
R
R
Bit
Position
Value
Description
2
[7:3]
00000–11111 5-bit I C status code.
STAT
[2:0]
000
Reserved.
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
