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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read/Write Address: 0004H  
Reset Value: 0000H  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
CKO4  
P
CKO4  
SEL  
CKO  
FPO3  
SEL1  
CKO  
FPO3  
SEL0  
CKO3  
P
FPO3  
P
FPO3  
POS  
CKO2  
P
FPO2  
P
FPO2  
POS  
CKO1  
P
FPO1  
P
FPO1  
POS  
CKO0  
P
FPO0  
P
FPO0  
POS  
Bit  
Name  
Description  
6
FPO2POS  
Output Frame Pulse (FPo2) Position  
When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS).  
When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus).  
5
CKO1P  
Output Clock (CKo1) Polarity Selection  
When this bit is low, the output clock CKo1 falling edge aligns with the frame  
boundary. When this bit is high, the output clock CKo1 rising edge aligns with the  
frame boundary.  
4
3
2
FPO1P  
FPO1POS  
CKO0P  
Output Frame Pulse (FPo1) Polarity Selection  
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.  
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.  
Output Frame Pulse (FPo1) Position  
When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS).  
When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus).  
Output Clock (CKo0) Polarity Selection  
When this bit is low, the output clock CKo0 falling edge aligns with the frame  
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the  
frame boundary.  
1
0
FPO0P  
Output Frame Pulse (FPo0) Polarity Selection  
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.  
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.  
FPO0POS  
Output Frame Pulse (FPo0) Position  
When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS).  
When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).  
Note: In Divided Slave modes, CKo3 - 1 cannot exceed frequency of CKi.  
Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set.  
Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)  
59  
Zarlink Semiconductor Inc.  
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