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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read Address: 0010H  
Reset Value: 0000H  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
OUT  
ERR  
IN  
ERR  
Bit  
Name  
Description  
15 - 2  
Unused  
Reserved  
In normal functional mode, these bits are zero.  
1
0
OUTERR  
INERR  
Output Error (Read Only)  
This bit is set high when the total number of output channels is programmed to be  
more than the maximum capacity of 4096, in which case the output channels beyond  
the maximum capacity should be disabled.  
This bit will be cleared automatically after programming is corrected.  
Input Error (Read Only)  
This bit is set high when the total number of input channels is programmed to be more  
than the maximum capacity of 4096, in which case the input channels beyond the  
maximum capacity should be disabled.This bit will be cleared automatically after pro-  
gramming is corrected.  
Table 23 - Internal Flag Register (IFR) Bits - Read Only  
External Read Address: 00011H  
Reset Value: 0000H  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
BER  
F15  
BER  
F14  
BER  
F13  
BER  
F12  
BER  
F11  
BER  
F10  
BER  
F9  
BER  
F8  
BER  
F7  
BER  
F6  
BER  
F5  
BER  
F4  
BER  
F3  
BER  
F2  
BER  
F1  
BER  
F0  
Bit  
15 - 0  
Name  
Description  
BERF[n]  
BER Error Flag[n]:  
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not  
zero.  
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.  
Note: [n] denotes input stream from 0 - 15.  
Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only  
61  
Zarlink Semiconductor Inc.  
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