ZL50022
Data Sheet
External Read Address: 00014H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
L31
BER
L30
BER
L29
BER
L28
BER
L27
BER
L26
BER
L25
BER
L24
BER
L23
BER
L22
BER
L21
BER
L20
BER
L19
BER
L18
BER
L17
BER
L16
Bit
15 - 0
Name
Description
BERL[n]
BER Receiver Lock[n]:
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 16 - 31.
Table 27 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
External Read/Write Address: 0040H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
0
3
0
2
0
1
0
ST4_
LIM
RFRE
DPLL
_IRM
Bit
Name
Description
15-6
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
5
ST4_LIM Stratum 4E Limits Select Bit
When this bit is high, the Stratum 4E limits are used for reference monitoring (i.e.
+/-64.713 ppm and +/-82.487 ppm over 10 seconds).When this bit is low, more relaxed
Relaxed Stratum 4E limits are used for reference monitoring (i.e. +/-240 ppm and
+/-250 ppm over 10 seconds). This is used in applications where a low quality clock
(+/-100 ppm) is used as a reference.
4-2
1
Unused
RFRE
Reserved
In normal functional mode, these bits MUST be set to zero.
Reference Frequency Register Enable
When this bit is low, the reference frequency value used in the DPLL comes from
appropriate reference frequency detector. When this bit is high, the reference frequency
value comes from Reference Frequency Register (RFR).
0
DPLL_
IRM
DPLL Internal Reset Mode
When this bit is low, the DPLL module is in the operational state. When this bit is high,
the DPLL module is in the power saving mode. Registers are not reset and are still
accessible in the power saving mode.
Table 28 - DPLL Control Register (DPLLCR) Bits
63
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
