ZL50022
Data Sheet
External Read/Write Address: 0001H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
STIO_
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
PD_EN
Bit
Name
Description
Memory Block Programming Start:
0
MBPS
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Table 18 - Internal Mode Selection Register (IMS) Bits (continued)
External Read/Write Address: 0002H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SRST
SW
SRST
DPLL
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
1
0
SRSTSW
Software Reset Bit for Switch
When this bit is low, data switching blocks are in normal operation. When this bit is
high, data switching blocks are in software reset state. Refer to Table 16, “Address
Map for Registers (A13 = 0)” on page 51 for details regarding which registers are
affected.
SRSTDPLL Software Reset Bit for DPLL
When this bit is low, the DPLL block is in normal operation. When this bit is high, the
DPLL block is in software reset state. Refer to Table 16, “Address Map for Registers
(A13 = 0)” on page 51 for details regarding which registers are affected.
Table 19 - Software Reset Register (SRR) Bits
56
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
