ZL50022
Data Sheet
External Read/Write Address: 0005H - 0007H
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
3
2
1
0
FP19
EN
FOF[n]
OFF7
FOF[n]
OFF6
FOF[n]
OFF5
FOF[n]
OFF4
FOF[n]
OFF3
FOF[n]
OFF2
FOF[n]
OFF1
FOF[n]
OFF0
FOF[n]
C1
FOF[n]
C0
Bit
Name
Description
15 - 11
10
Unused
FP19EN
Reserved. In normal functional mode, these bits MUST be set to zero.
19.44 MHz Frame Pulse Output Enable. (For FPo_OFF2 only)
This bit is a reserved bit for FPo_OFF0 and FPo_OFF1, and MUST be set to zero.
When this bit is high, FPo_OFF2 is negative frame pulse output corresponding to
19.44 MHz without channel offset.
When this bit is low, FPo_OFF2 is output frame pulse with channel offset.
FOF[n]OFF7 - 0
FOF[n]C1 - 0
9 - 2
1 - 0
FPo_OFF[n] Channel Offset
The binary value of these bits refers to the channel offset from original frame bound-
ary. Permitted channel offset values depend on bits 1-0 of this register.
FPo_OFF[n] Control bits
FOF[n]OFF7 - 0
FOF[n]C
1-0
Data Rate
(Mbps)
FPo_OFF[n]
Polarity
Control
Position
Control
Permitted
Pulse Cycle Width
Channel Offset
00
01
10
2.048
4.096
8.192
one 4.096 MHz clock
one 8.192 MHz clock
one 16.384 MHz
clock
0 - 31
0 - 63
0 - 127
FPO0P FPO0POS
FPO1P FPO1POS
FPO2P FPO2POS
11
16.384
one 16.384 MHz
clock
0 - 255
FPO2P FPO2POS
Note: [n] denotes output offset frame pulse from 0 to 2.
Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
60
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
