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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read/Write Address: 0001H  
Reset Value: 0000H  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
7
6
5
4
3
2
1
0
STIO_  
BDH  
BDL  
RBER  
EN  
TBER  
EN  
BPD  
2
BPD  
1
BPD  
0
MBPS  
PD_EN  
Bit  
Name  
Description  
Reserved. In normal functional mode, these bits MUST be set to zero.  
15 - 9  
8
Unused  
STIO_PD_ STio Pull-down Enable  
EN  
When this bit is low, the pull-down resistors on all STio pads will be disabled.  
When this bit is high, the pull-down resistors on all STio pads will be enabled.  
7
BDH  
Bi-directional Control for Streams 16-31  
BDH  
STio16 - 31 Operation  
0
normal operation:  
STi16-31 are inputs  
STio16-31 are outputs  
1
bi-directional operation:  
STi16-31 tied low internally  
STio16-31 are bi-directional  
6
BDL  
Bi-directional Control for Streams 0-15  
BDL  
STio0 - 15 Operation  
0
normal operation:  
STi0-15 are inputs  
STio0-15 are outputs  
1
bi-directional operation:  
STi0-15 tied low internally  
STio0-15 are bi-directional  
5
4
RBEREN  
TBEREN  
BPD2 - 0  
PRBS Receiver Enable  
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,  
this bit MUST be high.  
PRBS Transmitter Enable  
When this bit is low, all the BER transmitters are disabled. To enable any BER  
transmitters, this bit MUST be high.  
3 - 1  
Block Programming Data  
These bits refer to the value to be loaded into the connection memory, whenever the  
memory block programming feature is activated. After the MBPE bit in the Control  
Register is set to high and the MBPS bit in this register is set to high, the contents of  
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3  
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are  
zeroed.  
Table 18 - Internal Mode Selection Register (IMS) Bits  
55  
Zarlink Semiconductor Inc.  
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