ZL50022
Data Sheet
External Read/Write Address: 0004H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CKO4
P
CKO4
SEL
CKO
FPO3
SEL1
CKO
FPO3
SEL0
CKO3
P
FPO3
P
FPO3
POS
CKO2
P
FPO2
P
FPO2
POS
CKO1
P
FPO1
P
FPO1
POS
CKO0
P
FPO0
P
FPO0
POS
Bit
Name
Description
Output Clock (CKo4) Polarity Selection
15
CKO4P
When this bit is low, the output clock CKo4 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo4 rising edge aligns with the
frame boundary.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
14
CKO4SEL
Output Clock (CKo4) Frequency Selection
When this bit is low, the output clock CKo4 is 2.048 MHz.
When this bit is high, the output clock CKo4 is 1.544 MHz.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
13 - 12
CKOFPO3 Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle
SEL1 - 0 Selection
CKOFPO3
FPo3
CKo3
SEL1 - 0
00
01
10
11
244 ns
122 ns
61 ns
4.096 MHz
8.192 MHz
16.384 MHz
32.768 MHz
30 ns
11
CKO3P
Output Clock (CKo3) Polarity Selection
When this bit is low, the output clock CKo3 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo3 rising edge aligns with the
frame boundary.
10
9
FPO3P
FPO3POS
CKO2P
Output Frame Pulse (FPo3) Polarity Selection
When this bit is low, the output frame pulse FPo3 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo3 has the positive frame pulse format.
Output Frame Pulse (FPo3) Position
When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus).
8
Output Clock (CKo2) Polarity Selection
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
7
FPO2P
Output Frame Pulse (FPo2) Polarity Selection
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
58
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
