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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read/Write Address: 0003H  
Reset Value: 0000H  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
7
6
5
4
3
2
1
0
FPOF2  
EN  
FPOF1  
EN  
FPOF0  
EN  
CKO5  
EN  
CKO4  
EN  
CKO  
FPO3  
EN  
CKO  
FPO2  
EN  
CKO  
FPO1  
EN  
CKO  
FPO0  
EN  
Bit  
Name  
Description  
15 - 9  
Unused  
Reserved  
In normal functional mode, these bits MUST be set to zero.  
8
7
6
5
FPOF2EN  
FPOF1EN  
FPOF0EN  
CKO5EN  
FPo_OFF2/FPo5 Enable  
When this bit is high, output frame pulse FPo_OFF2/FPo5 is enabled.  
When this bit is low, output frame pulse FPo_OFF2/FPo5 is in high impedance state.  
FPo_OFF1 Enable  
When this bit is high, output frame pulse FPo_OFF1 is enabled.  
When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.  
FPo_OFF0 Enable  
When this bit is high, output frame pulse FPo_OFF0 is enabled.  
When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.  
CKo5 Enable  
When this bit is high, output clock CKo5 is enabled.  
When this bit is low, output clock CKo5 is in high impedance state.  
CKo5 is available in Master mode or in Slave mode with SLV_DPLLEN set.  
4
CKO4EN  
CKo4 Enable  
When this bit is high, output clock CKo4 is enabled.  
When this bit is low, output clock CKo4 is in high impedance state.  
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.  
3
2
1
0
CKOFPO3 CKo3 and FPo3 Enable  
When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.  
When this bit is low, CKo3 and FPo3 are in high impedance state.  
EN  
CKOFPO2 CKo2 and FPo2 Enable  
When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.  
When this bit is low, CKo2 and FPo2 are in high impedance state.  
EN  
CKOFPO1 CKo1 and FPo1 Enable  
When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.  
When this bit is low, CKo1 and FPo1 are in high impedance state.  
EN  
CKOFPO0 CKo0 and FPo0 Enable  
When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.  
When this bit is low, CKo0 and FPo0 are in high impedance state.  
EN  
Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits  
57  
Zarlink Semiconductor Inc.  
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