ZL50022
Data Sheet
External Read/Write Address: 0000H
Reset Value: 0000H
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLV_
OPM
1
OPM
0
CKi_
LP
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
DPLLEN
Bit
Name
Description
4
VAREN
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
3
2
MBPE
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
OSB
Output Stand By Bit:
This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table
describes the HiZ control of the serial data outputs:
RESET SRSTSW ODE
OSB
Bit
STio0 - 31
STOHZ0 - 15
Pin
(in SRR)
Pin
0
1
1
1
1
X
1
0
0
0
X
X
0
1
1
X
X
X
0
HiZ
HiZ
HiZ
HiZ
Driven High
Driven High
Driven High
Driven High
1
Active
(Controlled by CM)
Active
(Controlled by CM)
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 31
(bit2 - 0).
1 - 0
MS1 - 0
Memory Select Bits
These two bits are used to select connection memory low, connection high or data mem-
ory for access by CPU:
MS1 - 0
Memory Selection
00
01
10
11
Connection Memory Low Read/Write
Connection Memory High Read/Write
Data Memory Read
Reserved
Table 17 - Control Register (CR) Bits (continued)
54
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
