ZL38001
Data Sheet
External Read Address: 37H
Reset Value: 00H
7
6
5
4
3
2
1
0
SIPD15
SIPD14
SIPD13
SIPD12
SIPD11
SIPD10
SIPD9
SIPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SIPD15
SIPD14
SIPD113
SIPD12
SIPD11
SIPD10
SIPD9
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
SIPD8
Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2)
External Read Address: 38H
Reset Value: 00H
7
6
5
4
3
2
1
0
SEPD7
SEPD6
SEPD5
SEPD4
SEPD3
SEPD2
SEPD1
SEPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SEPD7
SEPD6
SEPD5
SEPD4
SEPD3
SEPD2
SEPD1
SEPD0
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1)
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
