ZL38001
Data Sheet
External Read Address: 19H
Reset Value: 00H
7
6
5
4
3
2
1
0
REPD15
REPD14
REPD13
REPD12
REPD11
REPD10
REPD9
REPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
REPD15
REPD14
REPD13
REPD12
REPD11
REPD10
REPD9
These peak detector registers allow the user to monitor the error signal peak
level at reference point R2 (see Figure 1). The information is in 16-bit 2’s
complement linear coded format presented in two 8-bit registers. The high
byte is in Register 2 and the low byte is in Register 1.
REPD8
Register Table 13 - Receive (Rin) ERROR Peak Detect Register 2 (REPD2)
External Read Address: 3AH
Reset Value: 00H
7
6
5
4
3
2
1
0
ROPD7
ROPD6
ROPD5
ROPD4
ROPD3
ROPD2
ROPD1
ROPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
ROPD7
ROPD6
ROPD5
ROPD4
ROPD3
ROPD2
ROPD1
ROPD0
These peak detector registers allow the user to monitor the receive out signal
(Rout) peak level at reference point R3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 14 - Receive (Rout) Peak Detect Register 1 (ROPD1)
37
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
