ZL38001
Data Sheet
External Read Address: 3BH
Reset Value: 00H
7
6
5
4
3
2
1
0
ROPD15
ROPD14
ROPD13
ROPD12
ROPD11
ROPD10
ROPD9
ROPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
ROPD15
ROPD14
ROPD13
ROPD12
ROPD11
ROPD10
ROPD9
ROPD8
These peak detector registers allow the user to monitor the receive out signal
(Rout) peak level at reference point R3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2)
External Read Address: 36H
Reset Value: 00H
7
6
5
4
3
2
1
0
SIPD7
SIPD6
SIPD5
SIPD4
SIPD3
SIPD2
SIPD1
SIPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SIPD7
SIPD6
SIPD5
SIPD4
SIPD3
SIPD2
SIPD1
SIPD0
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1)
38
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
