ZL38001
Data Sheet
External Read Address: 39H
Reset Value: 00H
7
6
5
4
3
2
1
0
SEPD15
SEPD14
SEPD13
SEPD12
SEPD11
SEPD10
SEPD9
SEPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SEPD15
SEPD14
SEPD13
SEPD12
SEPD11
SEPD10
SEPD9
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
SEPD8
Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2)
External Read Address: 1AH
Reset Value: 00H
7
6
5
4
3
2
1
0
SOPD7
SOPD6
SOPD5
SOPD4
SOPD3
SOPD2
SOPD1
SOPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SOPD7
SOPD6
SOPD5
SOPD4
SOPD3
SOPD2
SOPD1
SOPD0
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1)
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
