ZL38001
Data Sheet
External Read Address: 1BH
Reset Value: 00H
7
6
5
4
3
2
1
0
SOPD15
SOPD14
SOPD13
SOPD12
SOPD11
SOPD10
SOPD9
SOPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SOPD15
SOPD14
SOPD13
SOPD12
SOPD11
SOPD10
SOPD9
SOPD8
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2)
External Read Address: 24H
Reset Value: 80H
7
6
5
4
3
2
1
0
L0
-
-
-
-
-
-
-
Bit
Name
Description
7
L0
This bit is used in conjunction with Rout Limiter Register 2. (See description
below.)
6
5
4
3
2
1
0
-
-
-
-
-
-
-
RESERVED
Register Table 22 - Rout Limiter Register 1 (RL1)
41
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
