ZL38001
Data Sheet
External Read/Write Address: 31H
Reset Value: 21H
7
6
5
4
3
2
1
0
DTDT2
DTDT1
DTDT0
-
-
-
-
-
Bit
Name
Description
7
6
5
DTDT2
DTDT1
DTDT0
DTDT2, DTDT1, DTDT0 Value
DTDT
DTDT2, DTDT1, DTDT0 Value
DTDT
000
001
010
011
-12 dB
-6 dB
0 dB
100
101
110
111
+12 dB
+18 dB
+24 dB
+30 dB
+6 dB
4
3
2
1
0
-
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
Register Table 9 - Double Talk detection Threshold Register (DTDT)
External Read Address: 16H
Reset Value: 00H
7
6
5
4
3
2
1
0
RIPD7
RIPD6
RIPD5
RIPD4
RIPD3
RIPD2
RIPD1
RIPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
RIPD7
RIPD6
RIPD5
RIPD4
RIPD3
RIPD2
RIPD1
RIPD0
These peak detector registers allow the user to monitor the receive in signal
(Rin) peak level at reference point R1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1)
35
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
