ZL38001
Data Sheet
External Read/Write Address: 32H
Reset Value: 25H
7
6
5
4
3
2
1
0
HG2
HG1
HG0
DTGain
-
-
-
-
Bit
Name
Description
7
6
5
4
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
-
-
DTRGain
This bit controls the gain level at Rout during double talk. When this bit is high
12 dB of attenuation is injected into the Rout path during double talk. When
this bit is low the gain pad is disabled.
3
2
1
0
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1)
External Read/Write Address: 12H
Reset Value: 00H
7
6
5
4
3
2
1
0
-
-
-
DTSGain
-
-
Bit
Name
Description
7
6
5
4
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
-
-
DTSGain
This bit controls the gain level at Sout during double talk. When this bit is high
12 dB of attenuation is injected into the Sout path during double talk. When
this bit is low the gain pad is disabled.
3
2
1
0
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2)
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
