ZL30402
Data Sheet
Lock Indicator: Entry into Normal mode is flagged by the LOCK status bit or pin. Lock is declared when the
Acquisition PLL is locked to the reference clock and the Core PLL is locked to the Acquisition PLL. Frequency lock
means that the center frequency of the PLL is identical to the reference frequency and phase error excursions
caused by jitter and wander are symmetrical around some long-term phase error average.
Reference Re-alignment: Reference realignment is performed to erase a residual phase error that has been
accumulated between the reference and output clocks as a result of reference switching. A high to low transition on
the RefAlign pin (or bit) initiates phase realignment with a phase slope on the output clocks limited to 41 ns in 1.326
ms for the 1.1 Hz filter and to 885 ns in 1 s for 0.1 Hz filter. Please refer to the ZLAN-27 "Phase Alignment between
8 kHz output and 8 kHz Input Reference on ZL30402" Application Note for details.
2.3 Clock Synthesizer
The output of the Core PLL is connected to the Clock Synthesizer that generates twelve clocks and three frame
pulses.
2.4 Output Clocks
The ZL30402 provides the following clocks (see Figure 13 "ST-BUS and GCI Output Timing", Figure 14 "DS1, DS2
and C19o Clock Timing", Figure 15 "C155o and C19o Timing", and Figure 18 "E3 and DS3 Output Timing" for
details):
- C1.5o
- C2o
: 1.544 MHz clock with nominal 50% duty cycle
: 2.048 MHz clock with nominal 50% duty cycle
: 4.096 MHz clock with nominal 50% duty cycle
: 6.312 MHz clock with nominal 50% duty cycle
: 8.192 MHz clock with nominal 50% duty cycle
: 8.592 MHz clock with duty cycle from 30 to 70%.
: 11.184 MHz clock with duty cycle from 30 to 70%.
: 16.384 MHz clock with nominal 50% duty cycle
: 19.44 MHz clock with nominal 50% duty cycle (with optional dejittering)
: 34.368 MHz clock with nominal 50% duty cycle
: 44.736 MHz clock with nominal 50% duty cycle
: 155.52 MHz clock with nominal 50% duty cycle.
- C4o
- C6o
- C8o
- C8.5o
- C11o
- C16o
- C19o
- C34o
- C44o
- C155
The ZL30402 provides the following frame pulses (see Figure 13 "ST-BUS and GCI Output Timing" for details). All
frame pulses have the same 125 µs period (8kHz frequency):
- F0o
- F8o
- F16o
: 244 ns wide, logic low frame pulse
: 122 ns wide, logic high frame pulse
: 61 ns wide, logic low frame pulse
The Clock Synthesizer has an internal analog PLL (APLL) that can be placed in the path of the digitally generated
clocks to multiply frequencies and reduce jitter. The combination of two pins, E3DS3/OC3 and E3DS3, controls the
placement of the APLL and allows for selection of different clock configurations e.g., if E3DS3/OC3 pin is low the
19.44 MHz clock is derived from 155.52 MHz clock with very low jitter. The same APLL can be used to generate
clocks with E3, DS3 or OC3 rates (see Figure 4 "C19o, C155o, C34/C44 Clock Generation Options" for details).
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