ZL30402
Data Sheet
Pin Description (continued)
Pin #
Name
Description
74 - 77
D4 - D7
Data 4 to Data 7 (5 V tolerant three-state I/O). These signals combine with D0
- D3 form the bi-directional data bus of the processor interface (D7 is the most
significant bit).
78
R/W
Read/Write Strobe (5 V tolerant input). This input controls the direction of the
data bus D[0-7] during a microprocessor access. When R/W is high, the
parallel processor is reading data from the ZL30402. When low, the parallel
processor is writing data to the ZL30402.
79
80
A0
IC
Address 0 (5 V tolerant input). Address input for the microprocessor interface.
A0 is the least significant input.
Internal Connection (Input). Connect this pin to ground.
2.0 Functional Description
The ZL30402 is a Network Element PLL designed to provide timing for SDH and SONET equipment conforming to
ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates clocks for legacy PDH equipment
operating at DS1, DS2, DS3, E1, and E3 rates. The ZL30402 provides clocks for industry standard ST-BUS and
GCI backplanes, and it also supports H.110 timing requirements. The functional block diagram of the ZL30402 is
shown in Figure 1 "Functional Block Diagram" and its operation is described in the following section.
2.1 Acquisition PLLs
The ZL30402 has two Acquisition PLLs for monitoring availability and quality of the Primary (PRI) and Secondary
(SEC) reference clocks. Each Acquisition PLL operates independently and locks to the falling edges of one of the
three input reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz or to the rising edge of 19.44 MHz. The reference
frequency can be determined from reading the Acquisition PLL Status Register bits InpFreq1 and InpFreq0 (see
Table 16 "Primary Acquisition PLL Status Register (R)" and Table 17 "Secondary Acquisition PLL Status Register
(R)").
The Primary and Secondary Acquisition PLLs are designed to provide status information that identifies two levels of
reference clock quality. For clarity, only the Primary Acquisition PLL is referenced in the text, but the same applies
to the Secondary Acquisition PLL.
-
Reference frequency drifts more than ±30000 ppm or is lost completely. In response, the Primary Acquisition
PLL enters its own Holdover mode and indicates this by asserting the HOLDOVER bit in the Primary
Acquisition PLL Status Register (Table 16 "Primary Acquisition PLL Status Register (R)"). Entry into Holdover
forces the Core PLL into the Auto Holdover state.
-
Reference frequency drifts more than ±104 ppm. In response the Primary Acquisition PLL asserts the
Frequency Limit bit PAFL in its Primary Acquisition PLL Status Register (Table 16) indicating that the
reference frequency crossed the boundary of the capture range.
Outputs of both Acquisition PLLs are connected to a multiplexer (MUX), which allows selecting a reference signal
that guarantees better traceability to the Primary Reference Clock. This multiplexer channels binary words to the
Core PLL digital phase detector (instead of analog signals). Application of the digital phase detector in the Core
PLL eliminates quantization errors and improves phase alignment accuracy.
The bandwidth of the Acquisition PLL is much wider than the bandwidth of the following Core PLL. This feature
allows cascading Acquisition and Core PLLs without changing the transfer function of the Core PLL.
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