ZL30402
Data Sheet
MS2, MS1 == 01 OR
RefSel change
Ref: FAIL --> OK &
NORMAL
(LOCKED)
00
MS2, MS1 == 00 &
AHRD=1 &
MHR= 0-->1 then 1-->0
{MANUAL}
Ref: OK &
Ref: OK --> FAIL &
MS2, MS1 == 00
{AUTO}
Ref: FAIL --> OK &
MS2, MS1 == 00 &
AHRD=0 &
MS2, MS1 == 00
{AUTO}
MS2, MS1! = 10
RESET == 1
{AUTO}
AUTO
HOLD-
OVER
RefSel Change
FREE-
RUN
10
HOLD-
OVER
01
RESET
MS2, MS1 == 10 forces
unconditional return from
any state to Free-run
Notes:
==: equal
{AUTO}: Automatic transition
STATE
MS2, MS1
! =: not equal
AUTO HOLDOVER: Automatic Holdover
& =: AND Operation
0 --> 1: transition from 0 to 1
Figure 5 - ZL30402 State Machine
2.6.3 Reset State
The Reset State must be entered when ZL30402 is powered-up. In this state, all arithmetic calculations are halted,
clocks are stopped, the microprocessor port is disabled and all internal registers are reset to their default values.
The Reset state is entered by pulling the RESET pin low for a minimum of 1 µs. When the RESET pin is pulled back
high, internal logic starts a 500 µs initialization process before switching into the Free-run state (MS2, MS1 = 10).
2.6.4 Free-Run State (Free-Run mode)
The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this
occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. In
the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30402
Master Crystal Oscillator. When equipment is installed for the first time (or periodically maintained) the accuracy of
the Free-run clocks can be adjusted to within 1x10-12 by setting the offset frequency in the Master Clock Frequency
Calibration Register.
2.6.5 Normal State (Normal Mode or Locked Mode)
The Normal State is entered when a good quality reference clock from the network is available for synchronization.
The ZL30402 automatically detects the frequency of the reference clock (8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz) and sets the LOCK status bit and pin high after acquiring synchronization. In the Normal state all
generated clocks (C1.5o, C2o, C4o, C6o, C8o, C16o, C19o, C34/C44 and C155) and frame pulses (F0o, F8o,
F16o) are derived from network timing. To guarantee uninterrupted synchronization, the ZL30402 has two
Acquisition PLLs that continuously monitor the quality of the incoming reference clocks. This dual architecture
enables quick replacement of a poor or failed reference and minimizes the time spent in other states.
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
