ZL30402
Data Sheet
The compensation value for the Master Clock Calibration Register (MCFC3 to MCFC0) can be calculated from the
following equation:
MCFC = 45036 * ( - foffset) where: foffset = fm - 20 000 000 Hz
The fm frequency should only be measured after the Master Crystal Oscillator has been mounted inside a system
and powered long enough for the Master Crystal Oscillator to reach a steady operating temperature. Section 5.2 on
page 31 provides two examples of how to calculate an offset frequency and convert the decimal value to a binary
format. The maximum frequency compensation range of the MCFC register is equal to ±2384 ppm (±47680 Hz).
3.1 Microprocessor Interface
The ZL30402 can be controlled by a microprocessor or by an ASIC type of device that is connected directly to the
hardware control pins. If the HW pin is tied low (see Figure 6 "Hardware and Software Control options"), an 8-bit
Motorola type microprocessor may be used to control PLL operation and check its status. Under software control,
the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits.
The output pins LOCK and HOLDOVER are always active and they provide current status information whether the
device is in microprocessor or hardware control. Software (microprocessor) control provides additional functionality
that is not available in hardware control such as output clock phase adjustment, master clock frequency calibration
and extended access to status registers. These registers are also accessible when the ZL30402 operates under
Hardware control.
3.2 JTAG Interface
The ZL30402 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990,
which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made
up of four basic elements, Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers
(TDR) and all these elements are implemented on the ZL30402.
Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the
information required for a JTAG test system to access the ZL30402's boundary scan circuitry. The file is available
for download from the Zarlink Semiconductor web site: www.zarlink.com.
4.0 Hardware and Software Control
The ZL30402 offers Hardware and Software Control options that simplify design of basic or complex clock
synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing
cards without extensive programming. The complete set of control and status functions for each mode are shown in
Figure 6 "Hardware and Software Control options".
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Zarlink Semiconductor Inc.
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