欢迎访问ic37.com |
会员登录 免费注册
发布采购

ZL30402/QCC 参数 Datasheet PDF下载

ZL30402/QCC图片预览
型号: ZL30402/QCC
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH网元PLL [SONET/SDH Network Element PLL]
分类和应用: 电信集成电路异步传输模式ATM
文件页数/大小: 44 页 / 471 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号ZL30402/QCC的Datasheet PDF文件第5页浏览型号ZL30402/QCC的Datasheet PDF文件第6页浏览型号ZL30402/QCC的Datasheet PDF文件第7页浏览型号ZL30402/QCC的Datasheet PDF文件第8页浏览型号ZL30402/QCC的Datasheet PDF文件第10页浏览型号ZL30402/QCC的Datasheet PDF文件第11页浏览型号ZL30402/QCC的Datasheet PDF文件第12页浏览型号ZL30402/QCC的Datasheet PDF文件第13页  
ZL30402  
Data Sheet  
Pin Description (continued)  
Pin #  
Name  
Description  
35  
Tms  
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the  
state transition on the TAP controller. This pin is internally pulled up to VDD. If  
not used, this pin should be left unconnected.  
36  
37  
Tclk  
Trst  
IEEE1149.1a Test Clock Signal (5.5 V tolerant input). Input clock for the  
JTAG test logic. If not used, this pin should be pulled up to VDD.  
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG  
TAP controller. This pin should be pulsed low on power-up to ensure that the  
device in the normal functional state. This pin is internally pulled up to VDD. If  
not used, this pin should be connected to GND.  
38  
Tdi  
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test  
instructions and data. This pin is internally pulled up to VDD. If not used, this  
pin should be left unconnected.  
39  
40  
41  
42  
NC  
NC  
No internal bonding Connection. Leave unconnected.  
No internal bonding Connection. Leave unconnected.  
Internal Connection. Leave unconnected.  
IC  
C1.5o  
Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz  
DS1 rate clock.  
43  
C6o  
Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz  
DS2 rate clock.  
44  
45  
46  
IC  
Internal Connection. Connect this pin to Ground.  
Ground.  
GND  
C19o  
Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz  
clock.  
47  
RefSel  
Reference Source Select (Input). A logic low selects the PRI (primary)  
reference source as the input reference signal and logic high selects the SEC  
(secondary) input. The logic level at this input is sampled at the rising edge of  
F8o. This pin is internally pulled down to GND.  
48  
RefAlign  
Reference Align (Input). In Hardware Control a high to low transition at this  
input initiates phase realignment between the input reference and the  
generated output clocks. This pin is internally pulled down to GND.  
49  
50  
51  
VDD  
NC  
Positive Power Supply.  
No internal bonding Connection. Leave unconnected.  
C20i  
Clock 20 MHz (5.5 V tolerant input). This pin is the input for the 20 MHz  
Master Clock Oscillator.  
52  
GND  
Digital Ground.  
9
Zarlink Semiconductor Inc.