ZL30402
Data Sheet
2.6.6 Holdover State (Holdover Mode)
The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In
Holdover Mode, the ZL30402 generates clocks, which are not locked to an external reference signal but their
frequencies are based on stored coefficients in memory that were determined while the PLL was in Normal Mode
and locked to an external reference signal.
The initial frequency offset of the ZL30402 in Holdover Mode is 1x10-12. This is more accurate than Telcordia’s GR-
1244-CORE stratum 3E requirement of +1x10-9. Once the ZL30402 has transitioned into Holdover Mode, holdover
stability is determined by the stability of the 20MHz Master Clock Oscillator. Selection of the oscillator requires close
examination of the crystal oscillator temperature sensitivity and frequency drift caused by aging.
2.6.7 Auto Holdover State
The Auto Holdover state is a transitional state that the ZL30402 enters automatically when the active reference fails
unexpectedly. When the ZL30402 detects loss of reference it sets the HOLDOVER status bit and waits in Auto
Holdover state until the failed reference recovers. The HOLDOVER status may alert the control processor about the
failure and in response the control processor may switch to the secondary reference clock. The Auto Holdover and
Holdover States are internally combined together and they are output as a HOLDOVER status on pin 55 and bit 4 in
Status Register 1 (Table 6 on page 22).
2.6.8 State Transitions
In a typical Network Element application, the ZL30402 will typically operate in Normal mode (MS2, MS1 == 00)
generating synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs of
degraded quality and output status information for further processing. The status information from the Acquisition
PLLs and the CORE PLL combined with status information from line interfaces and framers (as listed below) forms
the basis for creating reliable network synchronization.
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•
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Acquisition PLLs (PAH, PAFL, SAH, SAFL) and
Core PLL (LOCK, HOLDOVER, FLIM)
Line interfaces (e.g. LOS - Loss of Signal, AIS - Alarm Indication Signal) and
Framers (e.g. LOF - Loss of frame or Synchronization Status Messages carried over SONET S1 byte or
ESF-DS1 Facility Data Link).
The ZL30402 State Machine is designed to perform some transitions automatically, leaving other less time
dependent tasks to the control processor. The state machine includes two stimulus signals which are critical to
automatic operation: “OK --> FAIL” and “FAIL --> OK” that represent loss (and recovery) of reference signal or its
drift by more than ±30000 ppm. Both of them force the Core PLL to transition into and out of the Auto Holdover
state. The ZL30402 State Machine may also be driven by controlling the mode select pins or bits MS2, MS1. In
order to avoid network synchronization problems, the State Machine has built-in basic protection that does not allow
switching the Core PLL into a state where it cannot operate correctly e.g. it is not possible to force the Core PLL into
Normal mode when all references are lost.
3.0 Master Clock Frequency Calibration Circuit
In an ordinary timing generation module, the Free-run mode accuracy of generated clocks is determined by the
accuracy of the Master Crystal Oscillator. If the Master Crystal Oscillator has a manufacturing tolerance of +/-
4.6 ppm, the generated clocks will have no better accuracy.
The ZL30402 eliminates tolerance problems by providing a programmable Master Clock Frequency Calibration
circuit, which can reduce oscillator manufacturing tolerance to near zero. This feature eliminates the need for high
precision 20 MHz crystal oscillators, which could be very expensive for equipment that has to maintain accuracy
over a very long period of time (e.g., 20 years in some applications).
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Zarlink Semiconductor Inc.
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