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ZL30402/QCC 参数 Datasheet PDF下载

ZL30402/QCC图片预览
型号: ZL30402/QCC
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH网元PLL [SONET/SDH Network Element PLL]
分类和应用: 电信集成电路异步传输模式ATM
文件页数/大小: 44 页 / 471 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30402  
C19o Output  
E3DS3/OC3  
Data Sheet  
C155 Output  
C34/44 Output  
E3DS3/OC3  
E3DS3/OC3  
0
0
0
1
1
1
19.44  
19.44  
0
11.184 44.736  
155.52  
HIZ  
Dejittered  
1
8.592  
34.368  
Figure 4 - C19o, C155o, C34/C44 Clock Generation Options  
All clocks and frame pulses except the C155 are output with CMOS logic levels. The C155 clock (155.52MHz) is  
output in a standard LVDS format.  
2.5 Output Clocks Phase Adjustment  
The ZL30402 provides three control registers dedicated to programming the output clock phase offset. Clocks  
C16o, C8o, C4o and C2o and frame pulses F16o, F8o, F0o are derived from 16.384 MHz and can be jointly shifted  
with respect to an active reference clock by up to 125 µs with a step size of 61 ns. The required phase shift of  
clocks is programmable by writing to the Phase Offset Register 2 ("Table 8") and to the Phase Offset Register 1  
("Table 9"). The C1.5o clock can be shifted as well in step sizes of 81ns by programming C1.5POA bits in Control  
Register 3 ("Table 11").  
The coarse phase adjustment is augmented with a very fine phase offset control on the order of 477 ps per step.  
This fine adjustment is programmable by writing to the Fine Phase Offset Register (Table 15 "Fine Phase Offset  
Register (R/W)"). The offset moves all clocks and frame pulses generated by ZL30402 including C155 clock.  
2.6 Control State Machine  
2.6.1 Clock Modes  
Any Network Element that operates in a synchronous network must support three Clock Modes: Free-run, Normal  
(Locked) and Holdover. These clock modes determine behavior of a Network Element to the unforeseen changes in  
the network synchronization hierarchy. Requirements for Clock Modes are defined in the international standards  
e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators. The  
ZL30402 supports all clock modes and each of these modes have a corresponding state in the Control State  
Machine.  
2.6.2 ZL30402 State Machine  
The ZL30402 Control State Machine is a complex combination of many internal states supporting the three  
mandatory clock modes. The simplified version of this state machine is shown in Figure 5 and it includes the  
mandatory states: Free-run, Normal and Holdover. These three states are complemented by two additional states:  
Reset and Auto Holdover, which are critical to the ZL30402 operation under the changing external conditions.  
14  
Zarlink Semiconductor Inc.  
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