P10C68/P11C68
STORE CYCLE 2 : E (BAR) CONTROLLED (See note 13)
P10C68-45
Symbol
P10C68-35
Min. Max.
10
0
0
Parameter
Units
Notes
17
Max.
Min.
Alternative
Standard
ms
ns
ns
ns
ns
Store cycle time
10
t
t
ELQX1
STORE
NE (bar) set-up to chip enable
Write enable wet-up to chip enable
Chip enable to NE (bar) rise
Output disable set-up to E (bar) fall
0
0
45
0
t
NLEL
t
t
t
WLEL
ELNH
GHEL
18
45
0
t
WC
NOTES
16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion.
17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted
by Vcc <3.3V (STORE inhibit).
18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all
inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.
NE
G
tGHNL
tNLWL
tWLNH
W
E
tELWL
tWLQX
HIGH IMPEDANCE
DQ
(DATA
OUT)
Figure 9. STORE CYCLE 1: W (bar) controlled timing diagram (see note 16).
tNLEL
NE
tGHEL
G
tWLEL
W
tELNH
E
tELQX1
DQ
(DATA
OUT)
HIGH IMPEDANCE
Figure 10. STORE CYCLE 2: E (bar) controlled timing diagram (see note 16).
9
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