P10C68/P11C68
tAVAV
ADDRESS
E
tEHICCL
tELQV
tELQX
tEHQZ
tGLQV
G
tGHQZ
tGLQX
DQ (DATA OUT)
ACTIVE
DATA VALID
tELICCH
ICC
STANDBY
W
tWHQV
F
igure 5. READ CYCLE 2 timing diagram (see note 9).
WRITE CYCLE 1 : W (BAR) CONTROLLED (See notes 8 and 13)
Commercial and Industrial Temperature Range
P10C68-45
P11C68-45
P10C68-35
P11C68-35
Max.
Symbol
Alternative
Units
Notes
Parameter
Min.
Max.
Min.
Standard
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
45
35
35
30
0
35
0
0
t
t
t
t
45
35
35
30
0
35
0
0
t
AVAV
WC
WP
CW
DW
DH
AW
t
WLWH
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address set-up to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
t
ELWH
DVWH
WHDX
AVWH
t
t
t
t
t
t
t
t
AVWL
AS
t
WHAX
WR
35
11, 14
35
t
t
t
WLQZ
WHQZ
WZ
5
t
5
OW
NOTES
13.
14.
E (bar) or W (bar) must be ≥ VIH during address transitions.
If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state.
6
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
