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P11C68-35IG 参数 Datasheet PDF下载

P11C68-35IG图片预览
型号: P11C68-35IG
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS / SNOS NVSRAM高性能为8K ×8非易失性静态RAM [CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 156 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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P10C68/P11C68  
tSKEW  
tAVAV  
tAVAV  
tAVAV  
INVALID  
ADDRESS 1  
ADDRESS 2  
ADDRESS 6  
ADDRESS  
tSTORE / t RECALL  
tAVQZ  
DATA VALID  
DQ  
(DATA  
OUT)  
HIGH  
IMPEDANCE  
DATA VALID  
DATA VALID  
DATA VALID  
Figure 14. STORE/RECALL cycle 1. Address controlled timing diagram (see notes 22, 26 and 27).  
tAVAV  
tAVAV  
ADDRESS  
ADDRESS 1  
ADDRESS 6  
tEHAX  
tAVEL  
tELEH  
E
tSTORE / t RECALL  
tELQZ  
DATA VALID  
DQ  
(DATA  
OUT)  
HIGH  
IMPEDANCE  
DATA VALID  
DATA VALID  
Figure 15. STORE/RECALL cycle 2. E (bar) controlled timing diagram (see notes 22, 25 and 27).  
OPERATING NOTES  
If the READ is initiated by E (bar) or G (bar), the outputs will  
be valid at tELQV or tGLQV, whichever is later. (READ CYCLE 2).  
The data outputs will repeatedly respond to address changes  
within the tAVQV access time without the need for transitions on  
any control input pins and will remain valid until another  
address change or until E (bar) or G (bar) is brought HIGH or  
W (bar) or NE (bar) is brought LOW.  
Note: References to NE (bar) should be taken as applying  
to P10C68 only and can be ignored for P11C68.  
The devices have two separate modes of operation: SRAM  
mode and non-volatile mode. In SRAM mode, the memory  
operates as an ordinary static RAM. While in non-volatile  
mode, data is transferred in parallel from SRAM to EEPROM  
or from EEPROM to SRAM.  
SRAM WRITE  
SRAM READ  
A write cycle is performed whenever E (bar) and W (bar)  
are LOW and NE (bar) is HIGH. The address inputs must be  
stable prior to entering the WRITE cycle and must remain  
stable until either E (bar) or W (bar) go HIGH at the end of the  
cycle. The data on the eight pins DQ0-7, will be written into the  
memory location specified by the address inputs if valid tDVWH  
before the end of a W (bar) controlled WRITE or tDVEH before  
the end of an E (bar) controlled WRITE.  
The devices perform a read cycle when ever E (bar) and G  
(bar) are LOW and NE (bar) and W (bar) are HIGH. The  
address specified by the thirteen address pins A0-12 determine  
which of the 8192 data bytes will be accessed. When the  
READ is initiated by an address transistion, the outputs will be  
valid after a delay of tAVQV (READ CYCLE 1).  
13