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P11C68-35IG 参数 Datasheet PDF下载

P11C68-35IG图片预览
型号: P11C68-35IG
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS / SNOS NVSRAM高性能为8K ×8非易失性静态RAM [CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 156 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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P10C68/P11C68  
P10C68 RECALL CYCLE 1 : NE (BAR) CONTROLLED (See note 16)  
P10C68-35  
Max.  
P10C68-45  
Symbol  
Alternative  
Parameter  
Units  
Notes  
Min.  
Max.  
Min.  
Standard  
19  
20  
Recall cycle time  
20  
µs  
µs  
ns  
ns  
ns  
ns  
20  
t
t
t
t
RECALL  
NLQX  
NLNH  
GLNL  
Recall initiation cycle time  
Output enable set-up  
Write enable set-up  
Chip enable set-up  
NE (bar) fall to output inactive  
25  
0
0
25  
0
0
t
RC  
t
WHNL  
0
0
t
t
ELNL  
NLQZ  
25  
25  
P10C68 RECALL CYCLE 2 : E (BAR) CONTROLLED (See note 16)  
P10C68-35  
Max.  
20  
25  
0
0
P10C68-45  
Symbol  
Parameter  
Units  
Notes  
Standard  
Min.  
Max.  
Min.  
Alternative  
19  
20  
t
t
Recall cycle time  
Recall initiation cycle time  
NE (bar) set-up  
Output enable set-up  
Write enable set-up  
µs  
ns  
ns  
ns  
ns  
20  
t
ELQX2  
RECALL  
25  
0
0
t
ELNH  
NLEL  
GLEL  
RC  
t
t
t
0
0
WHEL  
P10C68 RECALL CYCLE 3 : G (BAR) CONTROLLED (See note 16)  
P10C68-35  
Max.  
20  
25  
0
0
P10C68-45  
Symbol  
Parameter  
Units  
Notes  
Standard  
Min.  
Max.  
Alternative  
Min.  
19  
20  
t
t
µs  
ns  
ns  
ns  
ns  
Recall cycle time  
Recall initiation cycle time  
NE (bar) set-up  
Write enable set-up  
Chip enable set-up  
20  
t
GLQX2  
RECALL  
t
25  
0
0
GLNH  
NLGL  
WHGL  
ELGL  
RC  
t
t
t
0
0
NOTES  
19.  
Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Address transitions may not occur on  
any address pin during this time.  
20.  
Once t has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the RECALL cycle is completed automatically. Any  
RC  
of NE (bar), G (bar) or E (bar) may be used to terminate the RECALL initiation cycle.  
10