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P11C68-35IG 参数 Datasheet PDF下载

P11C68-35IG图片预览
型号: P11C68-35IG
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS / SNOS NVSRAM高性能为8K ×8非易失性静态RAM [CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 156 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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P10C68/P11C68  
tAVAV  
ADDRESS  
E
tWHAX  
tELWH  
tAVWH  
tWLWH  
tAVWL  
W
tDVWH  
tWHDX  
DATA IN  
DATA VALID  
tWHQX  
tWLQZ  
HIGH IMPEDANCE  
DATA OUT  
PREVIOUS DATA  
F
igure 6. WRITE CYCLE 1: W (bar) controlled timing diagram (see notes 8 and 13).  
WRITE CYCLE 2 : E (BAR) CONTROLLED (See notes 8 and 13)  
P10C68-45  
P11C68-45  
P10C68-35  
P11C68-35  
Max.  
Symbol  
Standard Alternative  
Units  
Notes  
Parameter  
Min.  
Max.  
Min.  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write cycle time  
Write pulse width  
45  
35  
35  
30  
0
35  
0
0
45  
35  
35  
30  
0
35  
0
0
t
t
t
t
t
WC  
WP  
CW  
DW  
AVAV  
t
WLEH  
Chip enable to end of write  
Data set-up to end of write  
Data hold after end of write  
Address set-up to end of write  
Address hold after end of write  
Address set-up to start of write  
t
t
t
ELEH  
DVEH  
EHDX  
t
DH  
AW  
WR  
t
t
t
t
t
AVEH  
EHAX  
AVWL  
t
AS  
tAVAV  
ADDRESS  
tAVEL  
tELEH  
tEHAX  
E
tAVEH  
tWLEH  
W
tDVEH  
DATA VALID  
tEHDX  
DATA IN  
HIGH IMPEDANCE  
DATA OUT  
F
igure 7. WRITE CYCLE 2: E (bar) controlled timing diagram (see notes 8 and 13).  
7