P10C68/P11C68
SRAM MEMORY OPERATION
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
Tamb = -40°C to + 85°C, Vcc = + 5V ꢀ 10%
READ CYCLES 1 AND 2 (See note 8)
P10C68-45
P11C68-45
P10C68-35
P11C68-35
Symbol
Units
Parameter
Notes
Min.
Max.
Max.
Min.
Standard
Alternative
Chip enable access time
Read cycle time
Address access time
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ACS
ELQV
35
9
10
45
t
t
RC
AVAV
35
20
45
25
t
t
AA
OE
OH
AVQV
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
t
t
t
GLQV
5
5
5
5
t
AXQX
t
t
LZ
ELQX
20
15
25
20
11
t
t
OHZ
EHQZ
0
0
0
0
t
t
OLZ
GLQX
11
12
12
t
t
t
t
HZ
PA
PS
GHQZ
t
t
ELICCH
EHICCL
25
45
25
55
t
t
WR
WHQV
NOTES
8.
E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be ≥ VIH during entire cycle.
For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
Device is continuously selected with E (bar) low, and G (bar) low.
Measured ꢀ200mV from steady state output voltage. Load capacitance is 5pF.
Parameter guaranteed but not tested.
9.
10.
11.
12.
tAVAV
ADDRESS
tAVQV
tAXQX
DQ (DATA OUT)
W
DATA VALID
tWHQV
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
5
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
