P10C68/P11C68
The P11C68 STORE cycle is initiated by executing
sequential READ cycles from six specific address locations.
By relying on READ cycles only, the P11C68 implements non-
volatile operation while remaining pin-for-pin compatible with
standard 8Kx8 SRAMs. During the STORE cycle, an erase of
the previous non-volatile data is first performed, followed by a
program of the non-volatile elements. The program operation
copies the SRAM data into non-volatile storage. Once a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed. Because a sequence of addresses
is used for STORE initiation, it is critical that no invalid address
states intervene in the sequence or the sequence will be
aborted. The maximum skew between address inputs A0-12
for each address state is tSKEW (STORE CYCLE 1).
It is recommended that G (bar) be kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G (bar) is left LOW, internal circuitry will
turn off the output buffers tWHQZ after W (bar) goes LOW.
Non-Volatile STORE - P10C68
A STORE cycle is performed when NE, (bar) E (bar) and W
(bar) are LOW and G (bar) is HIGH. While any sequence to
achieve this state will initiate a STORE, only W(bar) initiation
(STORE CYCLE 1) and E (bar) initiation (STORE CYCLE 2)
are practical without risking an unintentional SRAM WRITE
that would disturb SRAM data. During the STORE cycle,
previous non-volatile data is erased and the SRAM contents
are then programmed into non-volatile elements. Once a
STORE cycle is initiated, further input and output is disabled
If tSKEW is exceeded it is possible that the transitional data
state will be interpreted as a valid address and the sequence
will be aborted. If E (bar) controlled READ cycles are used for
the sequence (STORE CYCLE 2), address skew is no longer a
concern.
and the DQ
pins are tri-stated until the cycle is completed.
0-7
If E (bar) and G (bar) are LOW and W (bar) and NE (bar)
are HIGH at the end of the cycle, a READ will be performed
and the outputs will go active, signalling the end of the STORE.
To enable the STORE cycle the following READ sequence
must be performed.
The P10C68 will not be activated into either a STORE or
RECALL cycle by the software sequence required for the
P11C68.
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE Cycle
Hardware Protect - P10C68
The P10C68 offers two levels of protection to suppress
inadvertent STORE cycles. If the clock signals remain in the
STORE condition at the end of a STORE cycle, a second
STORE cycle will not be started. The STORE will be initiated
only after a HIGH to LOW transition on NE (bar)Because the
STORE cycle is initiated by an NE (bar) transition, powering-
up the chip with NE (bar) Low will not initiate a STORE cycle
either.
Once the sixth address in the sequence has been entered,
the STORE cycle will commence and the chip will be disabled.
It is important that READ cycles and not WRITE cycles be
used in the sequence, although it is not necessary that G (bar)
be LOW for the sequence to be valid. After the tSTORE cycle
time has been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
Once the first of the six reads has taken place, the read
sequence must either complete or terminate with an incorrect
address (other than 0000 hex) before it may be started anew.
In addition to multi-trigger protection, the P10C68 offers
hardware protection through Vcc Sense. A STORE cycle will
not be initiated, and one in progress will discontinue, if Vcc
goes below 3.3V.
Non-Volatile RECALL - P10C68
The P11C68 offers hardware protection against
inadvertent STORE cycles through Vcc Sense. A STORE
cycle will not be initiated, and one in progress will discontinue,
if Vcc goes below 3.3V.
A RECALL cycle is performed when E (bar), G (bar) and
NE (bar) are LOW and W (bar) is HIGH. Like the STORE cycle,
RECALL is initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL cycle will
take tNLQX to complete, during which all inputs are ignored.
When the RECALL completes, any READ or WRITE state on
the input pins will take effect.
Internally, RECALL is a two step procedure. First the
SRAM data is cleared and second, the non-volatile information
is transferred into the SRAM cells. The RECALL operation in
no way alters the data in the non-volatile cells. The non-volatile
data can be recalled an unlimited number of times. Address
transitions may not occur during the RECALL cycle. Like the
STORE cycle, a transition must occur on the NE (bar) pin to
cause a RECALL, preventing inadvertent multi-triggering. On
power-up, once Vcc exceeds Vcc sense voltage of 3.3V, a
RECALL cycle is automatically initiated. The voltage on the
Vcc pin must not drop below 3.3V once it has risen above it in
order for the RECALL to operate properly. Due to the
automatic RECALL, SRAM operation cannot commence until
tNLQX after Vcc exceeds 3.3V.
A RECALL of the EEPROM data into the SRAM is initiated
with a sequence of READ operations in a manner similar to the
STORE initiation. To initiate the RECALL cycle the following
sequence of READ operations must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second the non-volatile information
is transferred into the SRAM cells. The RECALL operation in
no way alters the data in the EEPROM cells. The non-volatile
data can be recalled an unlimited number of times. Address
transitions may not occur during the RECALL cycle.
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