MT90826
Data Sheet
Read/Write Address:
Reset value:
02H for DOS0 register,
03H for DOS1 register,
05H for DOS3 register,
07H for DOS5 register,
09H for DOS7 register,
04H for DOS2 register,
06H for DOS4 register,
08H for DOS6 register,
0000H for all DOS registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF33
IF32
IF31
IF30
IF22
IF21
IF20
IF12
IF11
IF10
IF02
IF01
IF41
IF81
IF00
IF23
IF13
IF03
DOS0 register
IF63
IF53
IF43
IF83
IF73
IF113
IF153
IF193
IF72
IF71
IF70
IF62
IF61
IF60
IF52
IF92
IF51
IF91
IF50
IF90
IF42
IF82
IF40
IF80
DOS1 register
IF112 IF111 IF110
IF152 IF151 IF150
IF192 IF191 IF190
IF103
IF102 IF101 IF100
IF93
DOS2 register
IF142 IF141 IF140 IF133
IF132 IF131 IF130 IF123
IF122 IF121 IF120
IF162 IF161 IF160
IF143
IF183
DOS3 register
IF173
IF163
IF182 IF181 IF180
IF172 IF171 IF170
DOS4 register
IF233 IF232 IF231 IF230 IF223
IF222 IF221 IF220 IF213 IF212 IF211 IF210 IF203 IF202 IF201 IF200
DOS5 register
IF272 IF271 IF270
IF262 IF261 IF260
IF252 IF251 IF250
IF242 IF241 IF240
IF273
IF263
IF253
IF243
DOS6 register
IF313 IF312 IF311 IF310 IF303 IF302 IF301 IF300 IF293 IF292 IF291 IF290 IF283 IF282 IF281 IF280
DOS7 register
Name (Note 1)
IFn3-0
Description
Input Offset Bits 3,2,1 & 0. These four bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STi pin: i.e., to start a new frame. The input
frame offset can be selected to +2.25 external clock periods (or 4.50 internal clock
cycles) from the point where the external frame pulse input signal is applied to the F0i
inputs of the device. See Table 9.
When the STi pin has a stream rate of 2.048 Mbps, the input offset cannot be adjusted
and the input offset bits have to be set to zero.
Table 8 - Frame Delay Offset Register (DOS) Bits
23
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
