MT90826
Data Sheet
Read/Write Address:
Reset Value:
0000H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
BPD2 BPD1 BPD0
CPLL CBER SBER SFE
0
BPE MBP
MS
OSB
0
Bit
Name
Description
4
MS
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
For data memory read operations, two consecutive microprocessor cycles are
required. The read address should remain the same for the two consecutive read
cycles. The data memory content from the first read cycle should be ignored. The
correct data memory content will be presented to the data bus on the second read
cycle.
3
OSB
Output Stand By. This bit controls the device output drivers.
OSB bit ODE pin OE bit STo0 - 31
0
1
1
0
X
1
0
1
1
1
X
0
Enable
Enable
1
Enable
0
High impedance state
Per-channel high impedance
X
2 - 0
DR2-0
Data Rate Select. Input/Output data rate selection. See next table (Table 6) for
detailed programming.
Table 5 - Control Register Bits (continued)
CLK
(CPLL=0)
CLK
(CPLL=1)
DR2
DR1
DR0
Serial Interface Mode
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
8 Mbps
16 Mbps
4 and 8 Mbps
16 and 8 Mbps
4 Mbps
16.384 MHz
16.384 MHz
16.384 MHz
8.192 MHz
2 and 4 Mbps
2 Mbps
16.384 MHz
8.192 MHz
Table 6 - Serial Data Rate Selections and External Clock Rates
20
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
