MT90826
Data Sheet
Frame Boundary
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
FEi Input
(FD[8:0] = 06H, frame offset of six C32i clock cycles)
(FD9 = 0, sample at internal C32i low phase)
For 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes
F0i
CLK
(16.384 MHz)
Internal
master clock
at 16 MHz
Offset Value
0
1
2
3
4
5
6
7
8
FEi Input
(FD[8:0] = 03H, frame offset of three C16i clock cycles)
(FD9 = 0, sample at internal C16i low phase)
For 4 Mbps and 2&4 Mbps modes
F0i
CLK
(16.384 MHz)
Internal
master clock
at 8 MHz
Offset Value
0
1
2
3
4
FEi Input
(FD[8:0] = 02H, frame offset of two C8i clock cycles)
(FD9 = 1, sample at internal C8i high phase)
For 2 Mbps mode
Figure 5 - Example for Frame Alignment Measurement
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
