MT90826
Data Sheet
Read/Write Address:
Reset Value:
0001H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FE4
FE3
FE2 FE1
FE0
CFE
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15 - 11
FE4-0
Frame Evaluation Input Select. The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
10
CFE
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
9
FD9
Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 5 for clock signal alignment.
Internal Master Clock
Operation Mode
2 Mbps
C8i
C16i
C32i
4 Mbps, 2&4 Mbps
8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps
8 - 0
FD8-0
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
Table 7 - Frame Alignment (FAR) Register Bits
21
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
