MT90826
Data Sheet
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
IFn=0000
8Mbps STi Stream
Bit 7
IFn=0100
Bit 7
8Mbps STi Stream
denotes the 3/4 point of the 8M bps bit cell
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
IFn=0000
IFn=0010
16Mbps STi Stream
Bit 7
Bit 7
16Mbps STi Stream
denotes the 1/2 point of the 16M bps bit cell
Figure 6 - Examples for Input Offset Delay Timing
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Zarlink Semiconductor Inc.