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MT90826AG 参数 Datasheet PDF下载

MT90826AG图片预览
型号: MT90826AG
PDF下载: 下载PDF文件 查看货源
内容描述: 四数字开关 [Quad Digital Switch]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 46 页 / 571 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT90826  
Data Sheet  
Read/Write Address:  
Reset value:  
000AH for FOR0 register,  
000BH for FOR1 register,  
000CH for FOR2 register,  
000DH for FOR3 register,  
0000H for all FOR registers.  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
OF71  
OF70  
OF61  
OF60  
OF51  
OF50  
OF41  
OF40  
OF31  
OF30  
OF21  
OF20  
OF11  
OF10  
OF01  
OF00  
FOR0 register  
OF151 OF150 OF141 OF140 OF131 OF130 OF121 OF120 OF111 OF110 OF101 OF100 OF91  
OF90  
OF81  
OF80  
FOR1 register  
OF231 OF230 OF221 OF220 OF211 OF210 OF201 OF200 OF191 OF190 OF181 OF180 O171  
OF170 OF161 OF160  
FOR2 register  
OF311 OF310 OF301 OF300 OF291 OF290 OF281 OF280 OF271 OF270 OF261 OF260 OF251 OF250 OF241 OF240  
FOR3 register  
Name  
Description  
(Note 1)  
OFn1, OFn0  
(n = 0 to 31)  
Output Offset Bits 1 - 0. These two bits define how soon the serial interface transmitter  
output the bit 0 from the STo pin. The output stream offset can be selected to -45 ns  
from the point where the external frame pulse input signal is applied to the F0i inputs of  
the device. See Table 11 and Figure 6.  
Table 10 - Frame Output Offset (FOR) Register Bits  
Corresponding Output Offset Bits  
Output Stream Offset for  
8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes  
(Not available for 2 Mbps, 4 Mbps and 2&4 Mbps modes)  
OFn1  
OFn0  
0
0
1
1
0
1
0
1
0 ns  
-15 ns  
-30 ns  
-45 ns  
Table 11 - Output Offset Bits (FD9, FD2-0)  
27  
Zarlink Semiconductor Inc.  
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