MT90826
Data Sheet
Measurement Result from
Frame Delay Bits
Corresponding Input Offset Bits
Input Stream
Offset
FD9
1
FD2
0
FD1
0
FD0
0
IFn3
0
IFn2
0
IFn1
0
IFn0
0
No internal master clock shift
(Default)
+ 0.5 internal master clock shift
+ 1.0 internal master clock shift
+ 1.5 internal master clock shift
+ 2.0 internal master clock shift
+ 2.5 internal master clock shift
+ 3.0 internal master clock shift
+ 3.5 internal master clock shift
+ 4.0 internal master clock shift
+ 4.5 internal master clock shift
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0)
25
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
