MT90826
Data Sheet
the device stops the bit error rate test and the internal bit error counter and transfers the error counts to the bit error
count register.
In the control register, a zero to one transition of the CBER bit resets the bit error count register and the internal bit
error counter.
The MT90826 does not recognize an input of all 1s as an error. If all 1s are being fed into the input stream and
channel, the BERT on chip BECR does not increment. This test is performed by sending defined data through the
message mode to ensure there is proper connectivity, and then running the BER test normally.
4.0 Delay Through the MT90826
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected by the TM bits in the
connection memory.
4.1 Variable Delay Mode (TM1=0, TM0=0)
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The delay through the switch can vary from 3 channels to 1 frame + 3
channels. The Variable delay is only available for odd number output streams but not for the even number output
streams. Avoid programming the TM0 and TM1 bits to zero in the connection memory when the destination output
streams are STo0, 2, 4, ..., 28 and 30.
4.2 Constant Delay Mode (TM1=1, TM0=0)
In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory
buffer. The delay through the switch is always two frames. The constant delay mode is available for all output
streams.
5.0 Microprocessor Interface
The MT90826 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is
compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0-
D15), 14-bit address bus (A0-A13) and 4 control lines (CS, DS, R/W and DTA). See Figure 16 for Motorola non-
multiplexed microport timing.
The MT90826 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and BECR registers which are read only.
For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13)
should remain the same for the two consecutive read cycles. The data memory content from the first read cycle
should be ignored.
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